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FEATURES Wide Bandwidth: 0.1 GHz to 2.5 GHz Min High Dynamic Range: 70 dB to 3.0 dB High Accuracy: 1.0 dB over 65 dB Range (@ 1.9 GHz) Fast Response: 40 ns Full-Scale Typical Controller Mode with Error Output Scaling Stable Over Supply and Temperature Wide Supply Range: +2.7 V to +5.5 V Low Power: 40 mW at 3 V Power-Down Feature: 60 W at 3 V Complete and Easy to Use APPLICATIONS RF Transmitter Power Amplifier Setpoint Control and Level Monitoring Logarithmic Amplifier for RSSI Measurement Cellular Base Stations, Radio Link, Radar PRODUCT DESCRIPTION
0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller AD8313
FUNCTIONAL BLOCK DIAGRAM
NINE DETECTOR CELLS + + + VPOS CINT INHI 8dB INLO EIGHT 8dB 3.5GHz AMPLIFIER STAGES INTERCEPT CONTROL COMM 8dB 8dB 8dB LP VvI VSET + + IvV VOUT
AD8313
VPOS SLOPE CONTROL BAND-GAP REFERENCE
GAIN BIAS
PWDN
The AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 dB and a -3 dB bandwidth of 3.5 GHz, for a total midband gain of 64 dB. At each amplifier output, a detector (rectifier) cell is used to convert the RF signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. The current-mode outputs of these cells are summed to generate a piecewise linear approximation to the logarithmic function, and converted to a low impedance voltagemode output by a transresistance stage, which also acts as a lowpass filter.
OUTPUT VOLTAGE - Volts DC
The AD8313 is a complete multistage demodulating logarithmic amplifier, capable of accurately converting an RF signal at its differential input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is -65 dBm to 0 dBm (re: 50 ), and the sensitivity can be increased by 6 dB or more with a narrow band input impedance matching network or balun. Application is straightforward, requiring only a single supply of 2.7 V-5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = +25C) amounts to only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 A) sleep mode, with a threshold at half the supply voltage.
When used as a log amp, the scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mV/dB; used as a controller, this stage accepts the setpoint input. The logarithmic intercept is positioned to nearly -100 dBm, and the output runs from about 0.45 V dc at -73 dBm input to 1.75 V dc at 0 dBm input. The scale and intercept are supply and temperature stable. The AD8313 is fabricated on Analog Devices' advanced 25 GHz silicon bipolar IC process and is available in a 8-lead SOIC package. The operating temperature range is -40C to +85C. An evaluation board is available.
2.0 FREQUENCY = 1.9GHz 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -80 -70 -60 -50 -40 -30 INPUT AMPLITUDE - dBm -20 -10 0 4 3 2 1 0 -1 -2 -3 -4 -5 5
Figure 1. Typical Logarithmic Response and Error vs. Input Amplitude
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
OUTPUT ERROR - dB
AD8313-SPECIFICATIONS (@ T = +25 C, V = +5.0 V , R 10 k
A S 1 L
unless otherwise noted)
2
Parameter SIGNAL INPUT INTERFACE Specified Frequency Range DC Common-Mode Voltage Input Bias Currents Input Impedance LOG (RSSI) MODE 100 MHz5 3 dB Dynamic Range6 Range Center 1 dB Dynamic Range Slope Intercept 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept Temperature Sensitivity 900 MHz5 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept Temperature Sensitivity 1.9 GHz 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept Temperature Sensitivity 2.5 GHz 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept 3 dB Dynamic Range Range Center 1 dB Dynamic Range Slope Intercept Temperature Sensitivity
7 7
Conditions
Min 0.1
Typ
Max2 2.5
Units GHz V A pF4
fRF < 100 MHz3
VPOS - 0.75 10 900 1.1
Sinusoidal, input termination configuration shown in Figure 27. Nominal Conditions 53.5 65 -31.5 56 17 19 -96 -88 +2.7 V VS +5.5 V, -40C T +85C 51 64 -31 55 16 19 -99 -89 PIN = -10 dBm -0.022 Nominal Conditions 60 69 -32.5 62 18 -93 68.5 -32.75 61 18 -95 -0.019 73 -36.5 62 17.5 -100 73 36.5 60 17.5 -101 -0.019 66 -34 46 20 -92 68 -34.5 46 20 -92 -0.040
21 -80
dB dBm dB mV/dB dBm dB dBm dB mV/dB dBm dB/C dB dBm dB mV/dB dBm dB dBm dB mV/dB dBm dB/C dB dBm dB mV/dB dBm dB dBm dB mV/dB dBm dB/C dB dBm dB mV/dB dBm dB dBm dB mV/dB dBm dB/C REV. B
22 -75
+2.7 V VS +5.5 V, -40C T +85C
15.5 -105 55.5
20.5 -81
15 -110 PIN = -10 dBm Nominal Conditions 52
21 -80
+2.7 V VS +5.5 V, -40C T +85C
15 -115 50
20.5 -85
14 -125 PIN = -10 dBm Nominal Conditions 48
21.5 -78
+2.7 V VS +5.5 V, -40C T +85C
16 -111 47
25 -72
14.5 -128 PIN = -10 dBm -2-
25 -56
AD8313
Parameter 3.5 GHz 3 dB Dynamic Range 1 dB Dynamic Range Slope Intercept CONTROL MODE Controller Sensitivity Low Frequency Gain Open-Loop Corner Frequency Open-Loop Slew Rate VSET Delay Time VOUT INTERFACE Current Drive Capability Source Current Sink Current Minimum Output Voltage Maximum Output Voltage Output Noise Spectral Density Small Signal Response Time Large Signal Response Time VSET INTERFACE Input Voltage Range Input Impedance POWER-DOWN INTERFACE PWDN Threshold Power-Up Response Time PWDN Input Bias Current POWER SUPPLY Operating Range Powered Up Current f = 900 MHz VSET to VOUT8 VSET to VOUT8 f = 900 MHz
5
Conditions
Min
2
Typ 43 35 24 -65 23 84 700 2.5 150
Max
2
Units dB dB mV/dB dBm V/dB dB Hz V/s ns
Open Loop Open Loop PIN = -60 dBm, fSPOT = 100 Hz PIN = -60 dBm, fSPOT = 10 MHz PIN = -60 dBm to -57 dBm, 10% to 90% PIN = No Signal to 0 dBm, Settled to 0.5 dB 0
400 10 50 VPOS - 0.1 2.0 1.3 40 110
60 160 VPOS
A mA mV V V/Hz V/Hz ns ns V pF V s A A
18k 1 VPOS/2 Time delay following HI to LO transition until device meets full specifications. PWDN = 0 V PWDN = VS +2.7 +4.5 V VS +5.5 V, -40C T +85C +2.7 V VS +3.3 V, -40C T +85C +4.5 V VS +5.5 V, -40C T +85C +2.7 V VS +3.3 V, -40C T +85C 13.7 1.8 5 <1 +5.5 15.5 18.5 18.5 150 50
Powered Down Current
50 20
V mA mA mA A A
NOTES 1 Except where otherwise noted, performance at V S = +3.0 V is equivalent to +5.0 V operation. 2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 3 Input impedance shown over frequency range in Figure 24. 4 Double slashes ( ) denote "in parallel with." 5 Linear regression calculation for error curve taken from -40 dBm to -10 dBm for all parameters. 6 Dynamic range refers to range over which the linearity error remains within the stated bound. 7 Linear regression calculation for error curve taken from -60 dBm to -5 dBm for 3 dB dynamic range. All other regressions taken from -40 dBm to -10 dBm. 8 AC response shown in Figure 10. Specifications subject to change without notice.
REV. B
-3-
AD8313
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V VOUT, VSET, PWDN . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS Input Power Differential (re: 50 , 5.5 V) . . . . . . . . . +25 dBm Input Power Single-Ended (re: 50 , 5.5 V) . . . . . . . +19 dBm Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 200 mW JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . +125C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
Pin 1, 4 2 3 5
Name VPOS INHI INLO PWDN
Description Positive supply voltage (VPOS), +2.7 V to +5.5 V. Noninverting Input. This input should be ac coupled. Inverting Input. This input should be ac coupled. Connect pin to ground for normal operating mode. Connect pin to supply for powerdown mode. Device Common. Setpoint input for operation in controller mode. To operate in RSSI mode, short VSET and VOUT. Logarithmic/Error Output.
6 7
COMM VSET
PIN CONFIGURATION
8
VPOS 1 INHI 2
8
VOUT
VOUT
VSET TOP VIEW INLO 3 (Not to Scale) 6 COMM
7
AD8313
VPOS 4
5
PWDN
ORDERING GUIDE
Model AD8313ARM AD8313ARM-REEL AD8313ARM-REEL7 AD8313-EVAL
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Descriptions 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel Evaluation Board
Package Option RM-08 RM-08 RM-08
Brand Code J1A J1A J1A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8313 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy [>250 V HBM] electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
Typical Performance Characteristics- AD8313
2.0 1.8 1.6 1.4 VS = +5V INPUT MATCH SHOWN IN FIGURE 27
2.0 1.8 1.6 1.4 VS = +5V INPUT MATCH SHOWN IN FIGURE 27 5 4 3 2 -40 C +25 C +85 C 1 0 -1 -2 -3 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -40 C AND +85 C -60 -50 -40 -30 -20 -10 INPUT AMPLITUDE - dBm 0 -4 -5 10
VOUT - Volts
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 INPUT AMPLITUDE - dBm -10 0 10 900MHz 1.9GHz 2.5GHz
1.2 1.0 0.8 0.6 0.4 0.2 0 -70
Figure 2. VOUT vs. Input Amplitude
Figure 5. VOUT and Log Conformance vs. Input Amplitude at 900 MHz; -40C, +25C and +85C
6 VS = +5V INPUT MATCH SHOWN IN FIGURE 27 4 900MHz 2 ERROR - dB 100MHz VOUT - Volts
2.0 1.8 1.6 -40 C 1.4 1.2 1.0 0.8 0.6 0.4 +25 C +85 C VS = +5V INPUT MATCH SHOWN IN FIGURE 27
5 4 3 2 1 0 -1 -2 -3 SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -40 C AND +85 C -60 -50 -40 -30 -20 -10 INPUT AMPLITUDE - dBm 0 -4 -5 10 ERROR - dB
0 2.5GHz 100MHz 1.9GHz -4
900MHz
-2
1.9GHz
2.5GHz
0.2 -6 -70 -60 -50 -40 -30 -20 INPUT AMPLITUDE - dBm -10 0 10
0 -70
Figure 3. Log Conformance vs. Input Amplitude
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz; -40C, +25C and +85C
2.0 1.8 1.6 1.4 VS = +5V INPUT MATCH SHOWN IN FIGURE 27
5 4 3 2
2.0 1.8 1.6 -40 C 1.4 VS = +5V INPUT MATCH SHOWN IN FIGURE 27
5 4 3 2 1 +25 C SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -40 C AND +85 C 0 -1 -2 -3 +85 C -4 -40 -30 -20 -10 INPUT AMPLITUDE - dBm 0 -5 10
ERROR - dB
1.2 1.0 0.8 0.6 0.4 0.2 0 -70
1 0
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60
+25 C +85 C
-1 -2 -3
SLOPE AND INTERCEPT NORMALIZED AT +25 C AND APPLIED TO -40 C AND +85 C -60 -50 -40 -30 -20 INPUT AMPLITUDE - dBm -10 0
-4 -5 10
-50
Figure 4. VOUT and Log Conformance vs. Input Amplitude at 100 MHz; -40C, +25C and +85C
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz; -40C, +25C and +85C
REV. B
-5-
ERROR - dB
VOUT - Volts
VOUT - Volts
-40 C
ERROR - dB
VOUT - Volts
100MHz
AD8313
22 VPS = +5V INPUT MATCH SHOWN IN FIGURE 27 21 +85 C -80 -70 VPS = +5V INPUT MATCH SHOWN IN FIGURE 27
SLOPE - mV/dB
20 +25 C 19 -40 C
INTERCEPT - dBm
+85 C -90 +25 C
18
-100 17 -40 C -110 0 500 1000 1500 FREQUENCY - MHz 2000 2500
16
0
500
1000 1500 FREQUENCY - MHz
2000
2500
Figure 8. VOUT Slope vs. Frequency; -40C, +25C and +85C
Figure 11. VOUT Intercept vs. Frequency; -40C, +25C and +85C
24 23 SPECIFIED OPERATING RANGE 22 2.5GHz 20 19 18 17 16 15 14 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE - V 5.5 6.0 1.9GHz 100MHz 900MHz
INTERCEPT - dBm
-70 -75 SPECIFIED OPERATING RANGE -80 -85 -90 -95 -100 -105 -110 2.5 2.5GHz 900MHz 1.9GHz
21 SLOPE - mV/dB
100MHz
3.0
3.5
4.0 4.5 5.0 SUPPLY VOLTAGE - V
5.5
6.0
Figure 9. VOUT Slope vs. Supply Voltage
Figure 12. VOUT Intercept vs. Supply Voltage
REF LEVEL = 92dB SCALE: 10dB/DIV
10 2GHz RF INPUT VS = +5.5V INPUT MATCH SHOWN IN FIGURE 27
VSET TO VOUT GAIN - dB
RF INPUT -70dBm -60dBm
V/ Hz
1
-55dBm -50dBm -45dBm -40dBm -35dBm -30dBm
100
1k
10k FREQUENCY - Hz
100k
1M
0.1 100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 10. AC Response from VSET to VOUT
Figure 13. VOUT Noise Spectral Density
-6-
REV. B
AD8313
100.00
CH. 1 & CH. 2: 200mV/DIV AVERAGE: 50 SAMPLES VS = +5.5V CH. 1 VS = +2.7V CH. 2 PULSED RF 100MHz, -45dBm
13.7mA
SUPPLY CURRENT - mA
10.00
1.00 VPOS = +3V 0.10 VPOS = +5V
CH. 1 GND CH. 2 GND
40 A 20 A 0.01 0 1 2 3 PWDN VOLTAGE - V 4 5
HORIZONTAL: 50ns/DIV
Figure 14. Typical Supply Current vs. PWDN Voltage
Figure 17. Response Time, No Signal to -45 dBm
CH. 1 & CH. 2: 1V/DIV
CH. 3: 5V/DIV
CH. 1 & CH. 2: 500mV/DIV
AVERAGE: 50 SAMPLES
VOUT @ VS = +5.5V CH. 1 GND VOUT @ VS = +2.7V CH. 2 GND
VS = +5.5V CH. 1 VS = +2.7V CH. 2 CH. 1 GND CH. 2 GND PULSED RF 100MHz, 0dBm
PWDN CH. 3 GND HORIZONTAL: 1 s/DIV
HORIZONTAL: 50ns/DIV
Figure 15. PWDN Response Time
Figure 18. Response Time, No Signal to +0 dBm
HP8648B 10MHz REF OUTPUT SIGNAL GENERATOR PIN = 0dBm RF OUT 10 +VS 0.01 F 0.01 F 10
4 VPOS PWDN 5 1 VPOS
EXT TRIG
HP8112A PULSE GENERATOR
OUT
HP8648B SIGNAL GENERATOR PULSE MODULATION MODE RF OUT
10MHz REF OUTPUT PULSE MODE IN
EXT TRIG OUT
HP8112A PULSE GENERATOR
TRIG OUT
VOUT 8 VSET 7 COMM 6
0.1 F
AD8313
2 INHI
TEK P6205 FET PROBE
TEK TDS784C SCOPE TRIG
-6dB RF SPLITTER -6dB +VS 10
1
VPOS INHI INLO
VOUT 8 VSET 7 COMM 6
54.9
3 INLO
0603 SIZE SURFACE MOUNT COMPONENTS ON A LOW LEAKAGE PC BOARD
0.01 F 0.01 F 10
0.1 F
2
AD8313
TEK P6205 FET PROBE
TEK TDS784C SCOPE TRIG
54.9
3
+VS
0603 SIZE SURFACE MOUNT COMPONENTS ON A LOW LEAKAGE PC BOARD
0.1 F
+VS
4
VPOS PWDN 5
0.1 F
Figure 16. Test Setup for PWDN Response Time
Figure 19. Test Setup for RSSI-Mode Pulse Response
REV. B
-7-
AD8313
CIRCUIT DESCRIPTION
2.0 1.8 1.6 1.4
VOUT - Volts
1.2 1.0 0.8 0.6
1 0 -1 -2 -3 INTERCEPT = -100dBm -4 -80 -70 -60 -50 -40 -30 INPUT AMPLITUDE - dBm -20 -10 0 -5
+ VPOS
NINE DETECTOR CELLS + +
+
+
IvV
VOUT
CINT INHI 8dB INLO EIGHT 8dB 3.5GHz AMPLIFIER STAGES INTERCEPT CONTROL COMM 8dB 8dB 8dB LP VvI VSET
0.4 0.2 0 -90
AD8313
VPOS SLOPE CONTROL BAND-GAP REFERENCE
Figure 21. Typical RSSI Response and Error vs. Input Power at 1.9 GHz
PWDN
GAIN BIAS
Figure 20. Block Diagram
A fully-differential design is used, and the inputs INHI and INLO (Pins 2 and 3) are internally biased to approximately 0.75 V below the supply voltage, and present a low frequency impedance of nominally 900 in parallel with 1.1 pF. The noise spectral density referred to the input is 0.6 nV/Hz, equivalent to a voltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of -76 dBm re: 50 . This sets the lower limit to the dynamic range; the Applications section shows how to increase the sensitivity by the use of a matching network or input transformer. However, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characteristic to partially compensate for errors due to internal noise. Each of the eight cascaded stages has a nominal voltage gain of 8 dB and a bandwidth of 3.5 GHz, and is supported by precision biasing cells which determine this gain and stabilize it against supply and temperature variations. Since these stages are direct-coupled and the dc gain is high, an offset-compensation loop is included. The first four of these stages, and the biasing system, are powered from Pin 4, while the later stages and the output interfaces are powered from Pin 1. The biasing is controlled by a logic interface PWDN (Pin 5); this is grounded for normal operation, but may be taken high (to VS) to disable the chip. The threshold is at VPOS/2 and the biasing functions are enabled and disabled within 1.8 s. Each amplifier stage has a detector cell associated with its output. These nonlinear cells essentially perform an absolute-value (full-wave rectification) function on the differential voltages along this backbone, in a transconductance fashion; their outputs are in current-mode form and are thus easily summed. A ninth detector cell is added at the input of the AD8313. Since the mid-range response of each of these nine detector stages is separated by 8 dB, the overall dynamic range is about 72 dB (Figure 21). The upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB, to the 3 dB error points. However, some erosion of this range will occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz (see Typical Performance Characteristics), needing only a small amount of additional ripple filtering. -8-
The fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and also by the output stage. The output stage converts these currents to a voltage, VOUT, at pin VOUT (Pin 8), which can swing "rail-torail." The filter exhibits a two-pole response with a corner at approximately 12 MHz and full-scale rise time (10%-90%) of 40 ns. The residual output ripple at an input frequency of 100 MHz has an amplitude of under 1 mV. The output can drive a small resistive load: it can source currents of up to 400 A, and sink up to 10 mA. The output is stable with any capacitive load, though settling time may be impaired. The low frequency incremental output impedance is approximately 0.2 . In addition to its use as an RF power measurement device (that is, as a logarithmic amplifier) the AD8313 may also be used in controller applications, by breaking the feedback path from VOUT to the VSET (Pin 7), which determines the slope of the output (nominally 18 mV/dB). This pin becomes the setpoint input in controller modes. In this mode, the voltage VOUT remains close to ground (typically under 50 mV) until the decibel equivalent of the voltage VSET is reached at the input, when VOUT makes a rapid transition to a voltage close to VPOS (see controller mode). The logarithmic intercept is nominally positioned at -100 dBm (re: 50 ) and this is effective in both the log amp mode and the controller mode. Thus, with Pins 7 and 8 connected (log amp mode) we have: VOUT = VSLOPE (PIN + 100 dBm) where PIN is the input power, stated in dBm when the source is directly terminated in 50 . However, the input impedance of the AD8313 is much higher than 50 and the sensitivity of this device may be increased by about 12 dB by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. This dependence on the choice of reference impedance can be avoided by restating the expression as: VOUT = 20 x VSLOPE x log (VIN/2.2 V) where VIN is the rms value of a sinusoidal input appearing across Pins 2 and 3; here, 2.2 V corresponds to the intercept, expressed in voltage terms. (For a more thorough treatment of the effect of signal waveform and metrics on the intercept positioning for a log amp, see the AD8307 data sheet). REV. B
ERROR - dB
The AD8313 is essentially an 8-stage logarithmic amplifier, specifically designed for use in RF measurement and power amplifier control applications at frequencies up to 2.5 GHz. A block diagram is shown in Figure 20. (For a full treatment of log-amp theory and design principles, consult the AD8307 data sheet).
5 SLOPE = 18mV/dB 4 3 2
AD8313
With Pins 7 and 8 disconnected (controller mode), the output may be stated as VOUT v VS VOUT v 0 when when VSLOPE (PIN + 100) > VSET VSLOPE (PIN + 100) < VSET
INHI 2 0.7pF INLO 3 0.5pF VPOS 4 1.25k GAIN BIAS (1ST DETECTOR) 250 1.24V VPOS 1 0.5pF 2.5k
~0.75V
2.5k
TO STAGES 1 THRU 4 125 125 1.25k TO 2ND STAGE
when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 . The transition zone between high and low states is very narrow, since the output stage behaves essentially as a fast integrator. The above equations may be restated as VOUT v VS VOUT v 0 when when VSLOPE log (VIN/2.2 V) > VSET VSLOPE log (VIN/2.2 V) < VSET
~1.4mA
COMM
Figure 23. Input Interface Simplified Schematic
A further use of the separate VOUT and VSET pins is in raising the load-driving current capability by the inclusion of an external NPN emitter follower. More complete information about usage in these various modes is provided in the Applications section.
INTERFACES
For high frequency use, Figure 24 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 trace and a 680 pF capacitor to ground from the INLO pin.
This section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit variations of up to 20%. These resistances are sometimes temperature dependent and the capacitances may be voltage dependent.
Power-Down Interface, PWDN
Frequency 100MHz 900MHz 1.9GHz 2.5GHz
R +j 650 -j 55 -j 22 -j 23 -j
X 400 135 65 43
100MHz
AD8313 MEASURED
900MHz
2.5GHz 1.9GHz 900 1.1pF
The power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 22. If Pin 5 is left unconnected or tied to the supply voltage (recommended) the bias enable current is shut off, and the current drawn from the supply is predominately through a nominal 300 k chain (20 A at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at VPOS/2. The input bias current at the PWDN pin when operating in the device "ON" state is approximately 5 A for VPOS = 3 V.
VPOS 4 50k 75k PWDN 5 150k TO BIAS ENABLE
Figure 24. Typical Input Impedance
Logarithmic/Error Output, VOUT
150k COMM 6
The rail-to-rail output interface is shown in Figure 25. VOUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current ISOURCE is limited by that provided by the PNP transistor, to typically 400 A. Larger load currents can be provided by adding an external NPN transistor (see Applications). The dc open-loop gain of this amplifier is high, and it may be regarded essentially as an integrator having a capacitance of 2 pF (CINT) driven by the current-mode signals generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 A/dB.
1 VPOS BIAS FROM SET-POINT SUMMED DETECTOR OUTPUTS LP LM 10mA MAX 6 CL I SOURCE 400 A CINT 8 VOUT
Figure 22. Power-Down Threshold Circuitry
Signal Inputs, INHI, INLO
gm STAGE
The simplest low frequency ac model for this interface consists of just a 900 resistance RIN in shunt with a 1.1 pF input capacitance, CIN connected across INHI and INLO. Figure 23 shows these distributed in the context of a more complete schematic. The input bias voltage shown is for the enabled chip; when disabled, it will rise by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a lowlevel signal transient to be introduced, having a time-constant formed by these capacitors and RIN. For this reason, largevalued coupling capacitors should be well matched; this is not necessary when using the small capacitors found in many impedance transforming networks used at high frequencies.
COMM
Figure 25. Output Interface Circuitry
Thus, for a midscale RF input of about 3 mV, which is some 40 dB above the minimum detector output, this current is 160 A and the output changes by 8 V/s. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for RL 10 k). The nominal slew rate is 2.5 V/s. The HF compensation technique results in stable operation with a large capacitive load, CL, though the positive-going slew rate will then be limited by ISOURCE/CL to 1 V/s for CL = 400 pF. -9-
REV. B
AD8313
Setpoint Interface, VSET
The setpoint interface is shown in Figure 26. The voltage VSET is divided by a factor of three in a resistive attenuator of total resistance 18 k. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 k), which balances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 x 4.0 A/dB x 1.5 k 18 mV/dB.
VPOS 1 25 A R1 12k VSET 8 FDBK 25 A TO O/P STAGE LP
R1 10 +VS 680pF 680pF R2 10 +VS
4 1
VPOS INHI INLO
VOUT 8 VSET 7 COMM 6
RPROT RL = 1M
0.1 F
2
AD8313
53.6
3
0.1 F
VPOS PWDN 5
Figure 27. Basic Connections for Log (RSSI) Mode
Operating in the Controller Mode
R2 6k R3 1.5k COMM 6
Figure 28 shows the basic connections for operation in controller mode. The link between VOUT and VSET is broken and a "setpoint" is applied to VSET. Any difference between VSET and the equivalent input power to the AD8313, will drive VOUT either to the supply rail or close to ground. If VSET is greater than the equivalent input power, VOUT will be driven towards ground and vice versa.
R1 10
1
Figure 26. Setpoint Interface Circuitry
+VS
RPROT VPOS INHI INLO VOUT 8 VSET 7 COMM 6 0.1 F
2
CONTROLLER OUTPUT VSETPOINT INPUT
APPLICATIONS Basic Connections for Log (RSSI) Mode
AD8313
Figure 27 shows the AD8313 connected in its basic measurement mode. A power supply of +2.7 V to +5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 F, surface mount ceramic capacitor and a series resistor of 10 . The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic "HI" at this pin. When disabled, the chip current is reduced to about 20 A from its normal value of 13.7 mA. The logic threshold is at VPOS/2 and the enable function occurs in about 1.8 s; note, however, that further settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 broadband resistive match, there are a wide variety of ways in which the input termination can be accomplished. These are discussed in the Input Coupling section. VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, RL, should not be lower than 5 k in order that the full-scale output of 1.75 V can be generated with the limited available current of 400 A max. As stated in the Absolute Maximum Ratings, an externally applied overvoltage on the VOUT pin that is outside the range 0 V to VPOS is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor (RPROT) should be included as shown. A 500 resistor is sufficient to protect against overvoltage up to 5 V; 1000 should be used if an overvoltage of up to 15 V is expected. Since the output stage is meant to drive loads of no more than 400 A, this resistor will not impact device performance for more high impedance drive applications (higher output current applications are discussed in the Increasing Output Current section).
3
R3 10 +VS
4
VPOS PWDN 5
0.1 F
Figure 28. Basic Connections for Operation in the Controller Mode
This mode of operation is useful in applications where the output power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 29). In this mode, a setpoint voltage, proportional in dB to the desired output power, is applied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313.
ENVELOPE OF TRANSMITTED SIGNAL
POWER AMPLIFIER RF IN DIRECTIONAL COUPLER
AD8313
VOUT RFIN VSET SETPOINT CONTROL DAC
Figure 29. Setpoint Controller Operation
VOUT is applied to the gain control terminal of the power amplifier. The gain control transfer function of the power amplifier should be an inverse relationship, i.e., increasing voltage decreases gain.
-10-
REV. B
AD8313
A positive input step on VSET (indicating a demand for increased power from the PA) will drive VOUT towards ground. This should be arranged to increase the gain of the PA. The loop will settle when VOUT settles to a voltage that sets the input power to the AD8313 to the dB equivalent of VSET.
Input Coupling
3 BALANCED 2 TERMINATED DR = 66dB
1
The signal may be coupled to the AD8313 in a variety of ways. In all cases, there must not be a dc path from the input pins to ground. Some of the possibilities include: dual input coupling capacitors, a flux-linked transformer, a printed-circuit balun, direct drive from a directional coupler, or a narrow-band impedance matching network. Figure 30 shows a simple broadband resistive match. A termination resistor of 53.6 combines with the internal input impedance of the AD8313 to give an overall resistive input impedance of approximately 50 . The termination resistor should preferably be placed directly across the input pins, INHI to INLO, where it serves to lower the possible deleterious effects of dc offset voltages on the low end of the dynamic range. At low frequencies, this may not be quite as attractive, since it necessitates the use of larger coupling capacitors. The two 680 pF input coupling capacitors set the high-pass corner frequency of the network at 9.4 MHz.
50 SOURCE 50 C1 680pF C2 680pF RMATCH 53.6
ERROR - dB
MATCHED 0
-1
BALANCED DR = 71dB
-2
MATCHED DR = 69dB
-3 -90
-80
-70
-60 -50 -40 -30 -20 INPUT AMPLITUDE - dBm
-10
0
10
Figure 31. Comparison of Terminated, Matched and Balanced Input Drive at 900 MHz
3 TERMINATED DR = 75dB 2 MATCHED 1
AD8313
CIN RIN
ERROR - dB
TERMINATED
0 BALANCED -1 MATCHED DR = 73dB
-2
BALANCED DR = 75dB
Figure 30. A Simple Broadband Resistive Input Termination
-3 -90
-80
-70
The high pass corner frequency can be set higher according to the equation:
f3 dB C1x C 2 where: C = C1+ C 2 1 = 2 x x C x 50
-60 -50 -40 -30 -20 INPUT AMPLITUDE - dBm
-10
0
10
Figure 32. Comparison of Terminated, Matched and Balanced Input Drive at 1900 MHz
A Narrow-Band LC Matching Example at 100 MHz
In high frequency applications, the use of a transformer, balun or matching network is advantageous. The impedance matching characteristics of these networks provide what is essentially a gain stage before the AD8313 that increases the device sensitivity. This gain effect is further explored in the following matching example. Figures 31 and 32 show device performance under these three input conditions at 900 MHz and 1900 MHz. While the 900 MHz case clearly shows the effect of input matching by realigning the intercept as expected, little improvement is seen at 1.9 GHz. Clearly, if no improvement in sensitivity is required, a simple 50 termination may be the best choice for a given design based on ease of use and cost of components.
While numerous software programs are available that allow the values of matching components to be easily calculated, a clear understanding of the calculations involved is valuable. A low frequency (100 MHz) value has been used for this exercise because of the deleterious board effects at higher frequencies. RF layout simulation software is useful when board design at higher frequencies is required. A narrow-band LC match can be implemented either as a series-inductance/shunt-capacitance or as a series-capacitance/ shunt-inductance. However, the concurrent requirement that the AD8313 inputs, INHI and INLO, be ac-coupled, makes a series-capacitance/shunt-inductance type match more appropriate (see Figure 33).
50 SOURCE 50
C1 LMATCH
AD8313
CIN RIN
C2
Figure 33. Narrow-Band Reactive Match
REV. B
-11-
AD8313
Typically, the AD8313 will need to be matched to 50 . The input impedance of the AD8313 at 100 MHz can be read from the Smith Chart (Figure 24) and corresponds to a resistive input impedance of 900 in parallel with a capacitance of 1.1 pF. To make the matching process simpler, the input capacitance of the AD8313, CIN, can be temporarily removed from the calculation by adding a virtual shunt inductor (L2), which will resonate away CIN (Figure 34). This inductor will be factored back into the calculation later. This allows the main calculation to be based on a simple resistive-to-resistive match (i.e., 50 to 900 ). The resonant frequency is defined by the equation = 1 L2 CIN therefore: L2 = 1 = 2.3 H 2 CIN
AD8313
L1 L2 CIN RIN
C1 and C2 can be chosen in a number of ways. First C2 can be set to a large value such as 1000 pF, so that it appears as an RF short. C1 would then be set equal to the calculated value of CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH so that the total series capacitance is equal to CMATCH. By making C1 and C2 slightly unequal (i.e., select C2 to be about 10% less than C1) but keeping their series value the same, the amplitude of the signals on INHI and INLO can be equalized so that the AD8313 is driven in a more balanced manner. Any one of the three options detailed above can be used as long as the combined series value of C1 and C2 (i.e., C1 x C2/(C1 + C2)) is equal to CMATCH. In all cases, the values of CMATCH and LMATCH must be chosen from standard values. At this point, these values need now be installed on the board and measured for performance at 100 MHz. Because of board and layout parasitics, the component values from the above example had to be tuned to the final values of CMATCH = 8.9 pF and LMATCH = 270 nH shown in Table I. Assuming a lossless matching network and noting conservation of power, the impedance transformation from RS to RIN (50 to 900 ) has an associated voltage gain given by GaindB = 20 x log RIN = 12.6 dB RS
50
SOURCE 50
C1
C2
CMATCH = LMATCH =
(C1 * C2) (C1 + C2) (L1 * L 2) (L1 + L 2)
TEMPORARY INDUCTANCE
Figure 34. Input Matching Example
With CIN and L2 temporarily out of the picture, the focus is now on matching a 50 source resistance to a (purely resistive) load of 900 and calculating values for CMATCH and L1. When RS RIN =
Because the AD8313 input responds to voltage and not true power, the voltage gain of the matching network will increase the effective input low-end power sensitivity by this amount. Thus, in this case, the dynamic range will be shifted downwards, that is, the 12.6 dB voltage gain will shift the 0 dBm to -65 dBm input range downwards to -12.6 dBm to -77.6 dBm. However, because of network losses this gain will not be fully realized in practice. Reference Figures 31 and 32 for an example of practical attainable voltage gains. Table I shows recommended values for the inductor and capacitors in Figure 32 for some selected RF frequencies along with the associated theoretical voltage gain. These values for a reactive match are optimal for the board layout detailed as Figure 45. As previously discussed, a modification of the board layout will produce networks that may not perform as specified. At 2.5 GHz, a shunt inductor is sufficient to achieve match. Consequently, C1 and C2 are set sufficiently high that they appear as RF shorts.
Table I. Recommended Values for C1, C2 and L MATCH in Figure 33
L1 C MATCH
the input will look purely resistive at a frequency given by fO = 1 2 L1 C MATCH = 100 MHz
Solving for CMATCH gives
C MATCH = 1 = 7.5 pF 2 fO RS RIN 1
Freq.
(MHz) 100 900 1900 2500
Solving for L1 gives L1 = RS RIN = 337.6 nH 2 fO
CMATCH (pF) 8.9 1.5 1.5 Large
C1 (pF) 22 9 3 1.5 3 1.5 390
C2 (pF) 15 1000 3 1000 3 1000 390
LMATCH (nH) 270 270 8.2 8.2 2.2 2.2 2.2
Voltage Gain (dB) 12.6 9.0 6.2 3.2
Because L1 and L2 are in parallel, they can be combined to give the final value for LMATCH (i.e.)
L MATCH =
L1 L2 = 294 nH L1 + L2
Figure 35 shows the voltage response of the 100 MHz matching network; note the high attenuation at lower frequencies typical of a high-pass network.
-12-
REV. B
AD8313
15
Table II. Values for REXT in Figure 37
Frequency MHz
10
VOLTAGE GAIN - dB
REXT k 0.953 2.00 2.55 0 29.4 32.4 33.2 26.7
Slope mV/dB 20 20 20 20 50 50.4 49.8 49.7
VOUT Swing for Pin -65 dBm to 0 dBm - V 0.44 to 1.74 0.58 to 1.88 0.70 to 2.00 0.54 to 1.84 1.10 to 4.35 1.46 to 4.74 1.74 to 4.98 1.34 to 4.57
5
0
100 900 1900 2500 100 900 1900 2500
100 FREQUENCY - MHz 200
-5 50
The value for REXT is calculated using the equation:
Figure 35. Voltage Response of 100 MHz Narrow-Band Matching Network
Adjusting the Log Slope
REXT =
(New Slope - Original Slope)
Original Slope
x 18 k
Figure 36 shows how the log slope may be adjusted to an exact value. The idea is simple: the output at pin VOUT is attenuated by the variable resistor R2 working against the internal 18 k of input resistance at the VSET pin. When R2 is zero, the attenuation it introduces is zero, and thus the slope is the basic 18 mV/dB (note that this value varies with frequency, see Figure 8). When R2 is set to its maximum value of 10 k, the attenuation from VOUT to VSET is the ratio 18/(18+10), and the slope is raised to (28/18) x 18 mV, or 28 mV/dB. At about the midpoint, the nominal scale will be 23 mV/dB. Thus, a 70 dB input range will change the output by 70 x 23 mV, or 1.6 V.
R1 10 0.1 F
The value for the Original Slope, at a particular frequency, can be read from Figure 8. The resulting output swing is calculated by simply inserting the New Slope value and the intercept at that frequency (Figures 8 and 11) into the general equation for the AD8313's output voltage: VOUT = Slope (PIN - Intercept)
Increasing Output Current
Where it is necessary to drive a more substantial load, one of two methods can be used. In Figure 38, a 1 k pull-up resistor is added at the output which provides the load current necessary to drive a 1 k load to +1.7 V for VS = 2.7 V. The pull-up resistor will slightly lower the intercept and the slope. As a result, the transfer function of the AD8313 will be shifted upwards (intercept shifts downward).
+VS R1 10 +VS
1 VPOS
+VS
1 VPOS
VOUT 8 VSET 7 R2 10k COMM 6
18-30mV/dB
AD8313
2 INHI
1k VOUT 8 VSET 7 COMM 6 20mV/dB RL = 1k
3 INLO
0.1 F
2
AD8313
INHI
R3 10 +VS
4 VPOS PWDN 5
0.1 F
3 INLO
R2 10
Figure 36. Adjusting the Log Slope
+VS
4 VPOS PWDN 5
0.1 F
As already stated, the unadjusted log slope varies with frequency from 17 mV/dB to 20 mV/dB, as shown in Figure 8. By placing a resistor between VOUT and VSET, the slope can be adjusted to a convenient 20 mV/dB as shown in Figure 37. Table II shows the recommended values for this resistor REXT. Also shown are values for REXT that increase the slope to approximately 50 mV/dB. The corresponding voltage swings for a -65 dBm to 0 dBm input range are also shown in Table II.
R1 10 +VS
1
Figure 38. Increasing AD8313 Output Current Capability
In Figure 39, an emitter-follower is used to provide current gain, when a 100 load can readily be driven to full-scale output. While a high transistor such as the BC848BLT1 (min = 200) is recommended, a 2 k pull-up resistor between VOUT and +VS can provide additional base current to the transistor.
R1 10 +VS
1
+VS
MIN
= 200
VPOS INHI INLO
VOUT 8 REXT VSET 7 COMM 6
20mV/dB
0.1 F
2
VPOS INHI INLO
VOUT 8 13k 10k VSET 7 COMM 6
BC848BLT1 OUTPUT RL 100
AD8313
0.1 F
2
AD8313
3
R3 10 +VS
4
3
VPOS PWDN 5
R3 10 +VS
4
0.1 F
VPOS PWDN 5
0.1 F
Figure 37. Adjusting the Log Slope to a Fixed Value
Figure 39. Output Current Drive Boost Connection
REV. B
-13-
AD8313
In addition to providing current gain, the resistor/potentiometer combination between VSET and the emitter of the transistor increases the log slope to as much as 45 mV/dB, at maximum resistance. This will give an output voltage of 4 V for a 0 dBm input. If no increase in the log slope is required, VSET can be connected directly to the emitter of the transistor.
Effect of Waveform Type On Intercept
Although it is specified for input levels in dBm (dB relative to 1 mW), the AD8313 fundamentally responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power but differing crest factors will produce different results at the log amp's output. The effect of different signal waveforms is to vary the effective value of the log amp's intercept upwards or downwards. Graphically, this looks like a vertical shift in the log amp's transfer function. The device's logarithmic slope, however, is in principle not affected. For example, consider the case of the AD8313 being alternately fed from a continuous wave and a single CDMA channel of the same rms power. The AD8313's output voltage will differ by the equivalent of 3.55 dB (64 mV) over the complete dynamic range of the device (the output for a CDMA input being lower). Table III shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A continuous wave input is used as a reference. To measure the rms power of a square-wave, for example, the mV equivalent of the dB value given in the table (18 mV/dB times 3.01 dB) should be subtracted from the output voltage of the AD8313.
Table III. Shift in AD8313 Output for Signals with Differing Crest Factors
The vacant portions of the signal and power layers are filled out with ground plane for general noise suppression. To ensure a low impedance connection between the planes, there are multiple through-hole connections to the RF ground plane. While the ground planes on the power and signal planes are used as general purpose ground returns, any RF grounds related to the input matching network (e.g., C2) are returned directly to the RF internal ground plane.
General Operation
The board should be powered by a single supply in the range, +2.7 V to +5.5 V. The power supply to each of the VPOS pins is decoupled by a 10 resistor and a 0.1 F capacitor. The two signal inputs are ac-coupled using 680 pF high quality RF capacitors (C1, C2). A 53.6 resistor across the differential signal inputs (INHI, INLO) combines with the internal 900 input impedance to give a broadband input impedance of 50.6 . This termination is not optimal from a noise perspective due to the Johnson noise of the 53.6 resistor. Neither does it take account for the AD8313's reactive input impedance or of the decrease over frequency of the resistive component of the input impedance. However, it does allow evaluation of the AD8313 over its complete frequency range without having to design multiple matching networks. For optimum performance, a narrowband match can be implemented by replacing the 53.6 resistor (labeled L/R) with an RF inductor and replacing the 680 pF capacitors with appropriate values. The section on Input Matching includes a table of recommended values for selected frequencies and explains the method of calculation. Switch 1 is used to select between power-up and power-down modes. Connecting the PWDN pin to ground enables normal operation of the AD8313. In the opposite position, the PWDN pin can either be driven externally (SMA connector labeled EXT ENABLE) to either device state or allowed to float to a disabled device state. The evaluation board ships with the AD8313 configured to operate in RSSI measurement mode, the logarithmic output appearing on the SMA connector labeled VOUT. This mode is set by the 0 resistor (R11), which shorts the VOUT and VSET pins to each other.
Varying the Logarithmic Slope
Signal Type CW Sine Wave Square Wave or DC Triangular Wave GSM Channel (All Time Slots On) CDMA Channel PDC Channel (All Time Slots On) Gaussian Noise
EVALUATION BOARD Schematic and Layout
Correction Factor (Add to Output Reading) 0 dB -3.01 dB +0.9 dB +0.55 dB +3.55 dB +0.58 dB +2.51 dB
Figure 44 shows the schematic of the evaluation board that was used to characterize the AD8313. Note that uninstalled components are drawn in as dashed. This is a 3-layer board (signal, ground and power), with a Duroid dielectric (RT 5880, h = 5 mil, R = 2.2). FR4 can also be used, but microstrip dimensions must be recalculated because of the different dielectric constant and board height. The trace layout and silkscreen of the signal and power layers are shown in Figures 40 to 43. A detail of the PCB footprint for the SOIC package and the pads for the matching components are shown in Figure 45.
The slope of the AD8313 can be increased from its nominal value of 18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 resistor, which shorts VSET to VOUT. VSET and VOUT are now connected through a 20 k potentiometer.
Operating in Controller Mode
To put the AD8313 into controller mode, R7 and R11 should be removed, breaking the link between VOUT and VSET. The VSET pin can then be driven externally via the SMA connector labeled EXT VSET IN ADJ.
Increasing Output Current
To increase the output current of VOUT, set both R3 and R11 to 0 and install potentiometer R4 (1 k to 5 k).
-14-
REV. B
AD8313
Figure 40. Layout of Signal Layer
Figure 42. Signal Layer Silkscreen
Figure 41. Layout of Power Layer
Figure 43. Power Layer Silkscreen
REV. B
-15-
AD8313
+VS SIG IN C2 680pF R2 10
4
R1 10 C1 680pF C3 0.1 F L/R 53.6
3 1
R5 0 VPOS VOUT 8 R11 0 R8 20k EXT VSET R7 0 R6 VOUT
AD8313
2
C6
INHI
VSET 7 COMM 6
INLO
+VS
C4 0.1 F
VPOS PWDN 5
R3 +VS
EXT ENABLE SW1
Figure 44. Evaluation Board Schematic
NOT CRITICAL DIMENSIONS
TRACE WIDTH 15.4
35 50
48 54.4 90.6 16 28 19 50 20 51 91.3 48 51.7 126 10
UNIT = MILS 41 22 75 20 27.5
46
Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC Package (RM-08)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
0.199 (5.05) 0.187 (4.75)
1 4
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
-16-
REV. B
PRINTED IN U.S.A.
C3390b-0-8/99
R4

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